1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory apparatus, e.g., an EPROM, an EEPROM or a mask ROM, adopting a reference method pertaining to the data reading. That is, this invention relates to a nonvolatile semiconductor apparatus comprising a memory circuit part equipped with a memory cell transistor, a reference circuit part equipped with a reference cell transistor, and a differential amplifier for outputting the content of the memory cell transistor by comparing the output from the memory cell transistor with the output from the reference cell transistor.
Generally, the operation of a nonvolatile semiconductor device can be speeded up by adopting a reference method, and a further speed up is possible with a reduction in noise effect in a differential amplifier.
2. Related Art
A nonvolatile semiconductor memory apparatus adopting a reference method has been proposed, as detailed in FIG. 1.
This nonvolatile semiconductor memory apparatus is an EPROM. It comprises a memory circuit part 1, a reference circuit part 2 and a differential amplifier 3, and reads out data by comparing the output voltage V.sub.MEM of the memory circuit part 1 with the output voltage V.sub.REF of the reference circuit part 2.
The memory circuit part 1 comprises a power source line 11 supplied with a power source voltage V.sub.CC, e.g. 5 V, an n channel MOS transistor (hereafter referred to as nMOS) 12 for a load, an nMOS 13 for bit line bias, a sense line SL, nMOS 14.sub.0 through 14.sub.m for bit line selection, bit lines BL.sub.0 through BL.sub.m, word lines WL.sub.0 through WL.sub.n and EPROM cells 15.sub.00 through 15.sub.nm making up a memory cell transistor.
nMOS 12 is a depletion type nMOS whose drain is connected with the power source line 11. Its gate and source are commonly connected, and its common connection point (hereafter referred to as node N.sub.MEM) is connected to one of the input terminals 31 of the differential amplifier 3 (turnover input terminal -) and a drain of nMOS 13.
nMOS's 13 and 14.sub.0 through 14.sub.m are enhancement type nMOS's. nMOS's 14.sub.0 through 14.sub.m, in particular, are the same size and have the same characteristics. Here, the source of nMOS 13 is connected to the drain of nMOS's 14.sub.0 through 14.sub.m via the sense line SL. The respective sources of nMOS's 14.sub.0 through 14.sub.m are connected to the drains of the first-line EPROM cells 15.sub.00 through the (n-1)th line 15.sub.n0, the drains of the second-line EPROM cells 15.sub.01 through the (n+1)th line 15.sub.n1, . . . , and the drains of the (m+1)th line EPROM cells 15.sub.0m through the (n+1)th line 15.sub.nm via bit lines BL.sub.0 through BL.sub.m.
The control gates of the first-line EPROM cells 15.sub.00 through the (m+1)th line 15.sub.0m, the second-line EPROM cells 15.sub.10 through the (m+1)th line 15.sub.1m, . . . , and the (n+1)th line EPROM cells 15.sub.n0 through the (m+1)th line 15.sub.nm are connected to word lines WL.sub.0 through WL.sub.n, and the sources of all the EPROM cells 15.sub.00 through 15.sub.nm are earthed.
EPROM cells 15.sub.00 through 15.sub.nm are all the same size. Their plan view and cross section are as shown in FIGS. 2 and 3. Here, 16 is a p type silicon substrate, 17 is a field oxide film, 15.sub.00C is a channel region, 18 and 19 are SiO.sub.2 (silicon dioxide) films, 15.sub.00FG is a floating gate, 15.sub.00CG is a control gate in the word line WL.sub.0, 15.sub.00 is a drain region, and 15.sub.00S is a source region.
This EPROM cell 15.sub.00 has a channel width W of 1.5 .mu.m (micro meters), a channel length L of 1.0 .mu.m (1 micrometer=10,000 angstroms), an overhang length A from the channel region 15.sub.00C of the floating gate 15.sub.00FG of 0.6 .mu.m, an oxide film thickness t.sub.CF between the control gate 15.sub.00CG and the floating gate 15.sub.00FG of 0.03 .mu.m (300 angstroms) and an oxide film thickness t.sub.FS between the floating gate 15.sub.00FG and the channel region 15.sub.00C, also of 0.03 .mu.m (300 angstroms).
Here, the capacitance C.sub.CF between the control gate 15.sub.00CG and the floating gate 15.sub.00FG is expressed as, ##EQU1## and the capacitance C.sub.FS between the floating gate 15.sub.00FG and the channel region 15.sub.00C is expressed as, ##EQU2## where .epsilon. SiO.sub.2 is the relative permittivity of SiO.sub.2 films 18 and 19, and .epsilon..sub.0 is the dielectric constant.
Also, the voltage V.sub.FG of the floating gate 15.sub.00FG is expressed as, ##EQU3## where V.sub.CG is the voltage of the control gate 15.sub.00FG and Q.sub.FG is the charge of the floating gate 15.sub.00FG. Therefore, if there is no charge in the floating gate 15.sub.00FG, ##EQU4## Substituting equations (1) and (2) into equation (4), ##EQU5## Substituting W=1.5 .mu.m and A=0.6 .mu.m into equation (5), EQU V.sub.FG =0.64 V.sub.CG ( 6)
Therefore, when V.sub.CG= 5 V, EQU V.sub.FG= 3.2 V
In the memory circuit part 1 thus configured, the gate of nMOS 13 is supplied with V.sub.BIAS, such as 2.5 V, and bit lines BL.sub.0 through BL.sub.m, i.e., the drains of EPROM cells 15.sub.00 through 15.sub.nm, are biased at about 1 V. This is purported to prevent a writing due to a so-called soft write phenomenon while data are read, if the drain voltages of EPROM cells 15.sub.00 through 15.sub.nm are too high.
Word lines WL.sub.0 through WL.sub.n are each supplied with word line selection signals X.sub.0 through X.sub.n so that a row is selected, and the gates of n MOS 14.sub.0 through 14.sub.m are each supplied with bit line selection signals Y.sub.0 through Y.sub.m so that a column is selected. These word-line selection signals X.sub.0 through X.sub.n and bit line selection signals Y.sub.0 through Y.sub.m are all either 5 V (the power source voltage V.sub.CC at a selection time) or 0 V (the earth voltage V.sub.SS at a non-selection time).
If the EPROM cell selected from among 15.sub.00 through 15.sub.nm memorizes the "ON" status, i.e., logical "1", a drain current flows through it. Conversely, if the selected EPROM cell memorizes the "OFF" status, i.e., logical "0", the drain current does not flow through it. Since nMOS's 12 and 13, as well as the nMOS selected from among 14.sub.0 through 14.sub.m and the EPROM cell selected from among 15.sub.00 through 15.sub.nm, configure a current-voltage conversion circuit, the existence of a drain current appears as a change in voltage V.sub.MEM of the node N.sub.MEM.
FIG. 4 shows the I.sub.DS -V.sub.FG characteristic of of EPROM cells 15.sub.00 through 15.sub.nm when the drain bias V.sub.DS is 1 V. When V.sub.FG =3.2 V in the "ON" status in this EPROM, as described earlier, I.sub.DS= 60 [.mu.A] (micro amperes).
The reference circuit part 2 comprises a power source line 21 supplied with a power voltage V.sub.CC, nMOS's 22 and 23 for a load, nMOS 24 for bit line bias, a reference sense line RSL, nMOS's 25.sub.0 through 25.sub.m for reference bit line selection (of which of nMOS's 25.sub.0 through 25.sub.m-1 are selected as dummy nMOS's), a reference bit line RBL, and EPROM cells 26.sub.0 through 26.sub.n making up a reference cell transistor.
nMOS's 22 and 23 are depletion type nMOS's the same size and having the same characteristics as nMOS 12. nMOS's 22 and 23 are connected in parallel. That is, their respective drains are connected to the power source line 21. Their respective gates and sources are commonly connected, and their respective common connection points (hereafter referred to as a node N.sub.REF) are connected to the other input terminal 32 (nonturnover input terminal +) of the differential amplifier 3 and the drain of nMOS 24.
nMOS 24 is an enhancement type nMOS of the same size and having the same characteristics as nMOS 13. The source of nMOS 13 is connected to the drains of nMOS's 25.sub.0 through 25.sub.m via the reference sense line RSL. nMOS's 25.sub.0 through 25.sub.m are enhancement type nMOS's the same size and having the same characteristics as nMOS's 14.sub.0 through 14.sub.m.
The sources of nMOS 25.sub.0 through 25.sub.m-1, are earthed, and the gates thereof are supplied with 0 V so that they are always in the "OFF" status. The source of nMOS 25.sub.m, however, is connected to the drains of EPROM cells 26.sub.0 through 26.sub.n via the reference bit line RBL, and the gates thereof are supplied with 5 V so that they are always in the "ON" status.
As for nMOS 13, the gate of nMOS 24 is supplied with V.sub.BIAS, e.g., 2.5 V, and the reference bit line RBL, i.e., the drains of EPROM cells 26.sub.0 through 26.sub.0, is biased at about 1 V.
EPROM cells 26.sub.0 through 26.sub.n are EPROM cells the same size and having the same characteristics as EPROM cells 15.sub.00 through 15.sub.nm. Their respective gates are connected to word lines WL.sub.0 through WL.sub.n and their respective sources are earthed. Electrons are not injected into the respective floating gates of EPROM cells 26.sub.0 through 26.sub.n, which are configured to be in the "ON" status when the power source voltage V.sub.CC is supplied to the control gate and to have the same drain current as that which flows when any of EPROM cells 15.sub.00 through 15.sub.nm of the memory circuit part 1 is turned to the "ON" status.
In the reference circuit part 2 thus configured, nMOS's 22, 23 and 24, plus any one of EPROM cells 26.sub.0 through 26.sub.n, configure a current-voltage conversion circuit. Since nMOS's 22 and 23 are parallel connected and their load resistance values are set at half that of the memory circuit part 1, the voltage V.sub.REF of the node N.sub.REF is set at the medium of the maximum and minimum values of the voltage V.sub.MEM of the node N.sub.MEM. Such an EPROM uses this voltage V.sub.REF as a reference voltage.
Because the node N.sub.MEM of the differential amplifier 3 is connected with one of the input terminals 31 (turnover input terminal -) and the node N.sub.REF thereof is connected with the other of the input terminals 32 (nonturnover input terminal +), when V.sub.MEM &gt;V.sub.REF the differential amplifier 3 outputs a low level "L" (the earth voltage 0 V) to its output terminal 33, and when V.sub.MEM &lt;V.sub.REF the differential amplifier 3 outputs a high level "H" (the power source voltage V.sub.CC). In this case, a voltage difference between V.sub.MEM and V.sub.REF of 50 mV suffices, and there is no need to change the output voltage from the memory circuit part 1 to either the high level "H" (power source voltage V.sub.CC) or the low level "L" (the earth voltage 0 V). In other words, if the node N.sub.MEM has a voltage change as low as 100 mV, data can be read out.
Therefore, access time of the EPROM adopting the reference method can shorten the access time.
Incidentally, in an EPROM adopting such a reference method, even when the voltage difference between V.sub.MEM and V.sub.REF is smaller than 50 mV, as long as the differential amplifier 3 can detect the difference, its response can be further speeded up. However, in an EPROM of the prior art, shown in FIG. 1, when data are read, since the memory circuit part 1 and the reference circuit part 2 configure asymmetric circuits, a difference arises between the stray capacitance to the input terminal 31 of the differential amplifier 3 and that to the input terminal 32 thereof. Therefore, when a noise generated from an output circuit (not shown in the drawing) is inputted to input terminals 31 and 32 of the differential amplifier 3, a difference arises between the levels of the noises respectively inputted to the two input terminals 31 and 32. As a result, if a further speed up of an action of a nonvolatile semiconductor memory apparatus is aimed at with a difference between V.sub.MEM and V.sub.REF smaller than e.g. 50 mV, the apparatus tends to be affected by noise and to read data erroneously. The problem is that no speed-up can be achieved unless this point is solved.
To solve such a problem, this invention provides a nonvolatile semiconductor memory apparatus which adopts a reference method having a higher action speed with a smaller level difference between the noise inputted to each of the two input terminals of the differential amplifier by making the stray capacitance to the memory circuit part and that of the reference circuit part as near equal as possible.